1. Field of the Invention
The present invention relates to a reception apparatus and method used in a digital radio communication system.
2. Description of the Related Art
In a recent radio communication field, improvement of spectral efficiency is required, and a digital communication system has been used widely as the main current because, for example, signal processing such as error correction and data compression can be simplified and the LSI therefor is easily available. A configuration of a transmission/reception apparatus adapted to the digital communication system is disclosed in, for example, Japanese Patent Gazette S55-79541.
With reference to FIG. 1, the following explains about a basic configuration and operation of a reception section in a convention digital transmission/reception apparatus. In FIG. 1, a received digital-modulated signal is subjected to quadrature frequency conversion in quadrature detection circuit 1 to be an in-phase baseband signal (I signal) and quadrature baseband signal (Q signal). An exemplary configuration of quadrature detection circuit 1 includes mixers 11 and 12, 90-degree phase shifter 13, oscillator 14 and filters 15 and 16.
A/D conversion circuit 2 performs quantization on the I signal based on a sampling clock output from clock generating circuit 6, and outputs a quantized digital I signal. Similarly A/D conversion circuit 3 performs quantization on the Q signal based on the sampling clock, and outputs a quantized digital Q signal. It is assumed in this example that the sampling clock is provided at a frequency integer times the symbol rate.
Timing estimating circuit 4 estimates a timing of a signal point of the digital-modulated signal using the digital I and Q signals each quantized at the sampling rate integer times the symbol rate. Digital demodulation circuit 5 performs demodulation using sampled data of the I signal and Q signal each closest to the signal point among data of the quantized I and Q signals, and outputs a demodulated data sequence.
According to the above configuration, timing synchronization and digital demodulation is performed using digital values quantized in A/D conversion circuits 2 and 3, and thereby a demodulated result is obtained. Adopting the above configuration makes it possible to perform digital processing in all the sections after A/D conversion circuits 2 and 3, and therefore provides a merit that the LSI therefor is easily available.
As the ratio (hereinafter referred to as oversampling number) of the frequency of sampling clock provided to A/D conversion circuits 2 and 3 to the symbol rate is increased, the provability that sampling is performed at a point close to an ideal signal point becomes higher. Accordingly an increased oversampling number enables timing estimating circuit 4 to perform timing estimation with high accuracy, and thereby improves reception sensitivity performance in digital demodulation circuit 5.
However the increased oversampling number requires high operation performance in A/D conversion circuits 2 and 3, thereby increasing current consumption and also increasing the cost. Therefore the oversampling number is usually determined in consideration of a balance of required specification, cost and others in each communication system.
Further in the case where the conventional digital transmission/reception apparatus illustrated in FIG. 1 is applied as a terminal in a communication system requiring transmission/reception timing with extremely high accuracy, it is necessary for a terminal side to acquire timing synchronization with high accuracy on a downlink digital-modulated signal transmitted from a base station side in the system, and to determine a timing of uplink transmission based on the obtained timing information. In order to perform the timing synchronization with high accuracy, it is generally necessary to set the oversampling number in the A/D conversion circuit to be large. For example, in the case of a communication system requiring timing accuracy of ± 1/32 times the symbol duration, the oversampling number equal to or more than 32 times the symbol rate is required in the A/D conversion circuit. This condition introduces excessive performance for an ordinary digital demodulator to obtain sufficient reception sensitivity performance, and provides demerits such as increased current consumption and increased cost in a configuration of the terminal.
Meanwhile a recently increased transmission rate in communications makes it impossible to greatly increase the ratio of the sampling rate in the A/D conversion circuit to the symbol rate. In this case, demodulation in reception is performed using a signal sampled at a timing shifted from an ideal reception timing. For example, in the case where demodulation in reception is performed while sampling a digital-modulated signal transmitted with a Nyquist filter at an oversampling rate twice the symbol rate, the demodulation in reception is performed using a signal sampled at a timing shifted maximum ±¼T with respect to the ideal reception timing, i.e., timing of a Nyquist point.
Thus in order to increase the timing estimation accuracy, such a method is considered that increases the sampling rate in the A/D conversion circuit. This method however causes power consumption and circuit scale in the terminal both to be increased.